Electrostatic protection circuit
US7291870B2 · kind B2 · utility
2Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Jul 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
Abstract
An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.