Integrated circuit having a resistive memory
US7292466B2 · kind B2 · utility
19Cited by
8References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 3, 2006 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a first resistive memory cell, a current source configured to provide an input current indicating a desired resistance level for the first memory cell, and a current mirror that mirrors the input current to provide an output current. The memory includes a first switching circuit configured to pass the output current to the first memory cell with the first memory cell not at the desired resistance level, and block the output current from the first memory cell in response to the first memory cell achieving the desired resistance level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.