Memory device with multistage sense amplifier

US7292479B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Sven Boldt · Aschheim, DE
• Erwin Thalmann · Birkenfeld, DE

Key dates

• Filing date: Jun 15, 2005
• Grant date: Nov 6, 2007
• Expiry date: Oct 24, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/26
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier. Binary data signals read out from the memory cell are amplified and evaluated. The binary data signals can also be written back to the corresponding memory cell. Furthermore, an output unit for outputting the amplified and evaluated binary data signals and a coupling device between the memory cell array and the sense amplifier are provided. The coupling device has a preamplifier unit for preamplifying the data signals read out and a bridging unit for bridging the preamplifier unit in order to provide a writing back of the binary data signals to the memory cell of the memory cell array.