Independent polling for multi-page programming
US7292487B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2006 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | May 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.