Feed forward equalizer and a method for analog equalization of a data signal
US7292631B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2004 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Mar 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A feed forward equalizer for analog equalization of a data signal received over a data transmission channel comprising a Master Delay Locked Loop (MDLL) for generating equidistant reference phase signals; a Slave Delay Line (SDL) formed by serial connected Slave Delay Units (SDU), wherein each Slave Delay Unit (SDU) has a Slave Delay Element (SDE) to delay the received data signal with a predetermined delay time (ΔT) and an analog amplifier which amplifies the delayed output signal of the Slave Delay Element (SDE) with a respective weighting coefficient to generate a weighted delay signal, wherein the analog amplifier is switched transparent in response to a corresponding reference phase signal generated by said Master Delay Locked Loop (M-DLL); and subtracting means for subtracting the weighted delay signals which are selected by means of a multiplexer from the received data signal to generate an equalized output data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.