Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency
US7293163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2004 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other hand, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode. If it determines to do so, the system resumes execution in the execute-ahead mode, and otherwise resumes execution in a non-aggressive mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.