Sherman H. Yip
23Patents
9h-index
8Co-inventors
60Inventor score
Filing activity: Oct 15, 2003 → Apr 27, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8041900B2 | Method and apparatus for improving transactional memory commit latency | Physics | 70 | Active |
| US7617421B2 | Method and apparatus for reporting failure conditions during transactional execution | Physics | 62 | Active |
| US8327188B2 | Hardware transactional memory acceleration through multiple failure recovery | Physics | 59 | Active |
| US7461208B1 | Circuitry and method for accessing an associative cache with parallel determination of data and data availability | Physics | 58 | Expired |
| US8984264B2 | Precise data return handling in speculative processors | Physics | 34 | Active |
| US7480787B1 | Method and structure for pipelining of SIMD conditional moves | Physics | 24 | Expired |
| US7293163B2 | Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency | Physics | 18 | Expired |
| US8732438B2 | Anti-prefetch instruction | Physics | 9 | Active |
| US7331039B1 | Method for graphically displaying hardware performance simulators | Emerging Cross-Sectional Technologies | 9 | Expired |
| US8364900B2 | Pseudo-LRU cache line replacement for a high-speed cache | Emerging Cross-Sectional Technologies | 3 | Active |
| US7418581B2 | Method and apparatus for sampling instructions on a processor that supports speculative execution | Physics | 3 | Active |
| US7610474B2 | Mechanism for hardware tracking of return address after tail call elimination of return-type instruction | Physics | 2 | Expired |
| US7650487B2 | Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency | Physics | 2 | Expired |
| US7634639B2 | Avoiding live-lock in a processor that supports speculative execution | Physics | 2 | Expired |
| US7757068B2 | Method and apparatus for measuring performance during speculative execution | Physics | 2 | Active |
| US7716457B2 | Method and apparatus for counting instructions during speculative execution | Physics | 2 | Active |
| US8065485B2 | Method and apparatus for determining cache storage locations based on latency requirements | Physics | 1 | Active |
| US8688963B2 | Checkpoint allocation in a speculative processor | Physics | 1 | Active |
| US9086889B2 | Reducing pipeline restart penalty | Physics | 1 | Active |
| US8181002B1 | Merging checkpoints in an execute-ahead processor | Physics | 1 | Active |
| US7257700B2 | Avoiding register RAW hazards when returning from speculative execution | Physics | 1 | Expired |
| US8316366B2 | Facilitating transactional execution in a processor that supports simultaneous speculative threading | Physics | 0 | Active |
| US8572356B2 | Space-efficient mechanism to support additional scouting in a processor using checkpoints | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.