Semiconductor contact device and method
US7294567B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.