Components, methods and assemblies for stacked packages
US7294928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2003 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Feb 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.