Integrated electronic non-volatile memory device having nand structure
US7295472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2006 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.