Method of making strained channel CMOS transistors having lattice-mismatched epitaxial
US7297583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jan 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a first single-crystal semiconductor region having a first composition. A stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a single-crystal semiconductor layer having a second composition such that the single-crystal semiconductor layer is lattice-mismatched to the first region. The semiconductor layer is formed over the source and drain regions and optionally over the extension regions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or the semiconductor layer having the second composition is not formed at all in the NFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.