Method for fabricating an integrated circuit on a semiconductor substrate

US7297983B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Hecht · Dresden, DE
• Henry Bernhardt · Dresden, DE
• Christian Kapteyn · Dresden, DE

Key dates

• Filing date: Dec 29, 2005
• Grant date: Nov 20, 2007
• Expiry date: Dec 29, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.