Charge-trapping memory cell and method for production

US7298004B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Specht · Munich, DE
• Wolfgang Roesner · Austin, US
• Franz Hofmann · Munich, DE

Key dates

• Filing date: Nov 30, 2004
• Grant date: Nov 20, 2007
• Expiry date: Mar 31, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6211
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.