Dram cell pair and dram memory cell array

US7301192B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Johann Harter · Dresden, DE
• Wolfgang Mueller · Garden City, US
• Wolfgang Bergner · Waldbüttelbrunn, DE
• Ulrike Grüning Von Schwerin · Birkenfeld, DE
• Till Schloesser · Dresden, DE
• Rolf Weis · Dresden, DE

Key dates

• Filing date: Sep 8, 2005
• Grant date: Nov 27, 2007
• Expiry date: Sep 8, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.