Asymmetric precharged flip flop
US7301373B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Dec 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45644
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either an output side or reference side of the differential stage is discharged. Also, during the evaluation phase, the latch stage write port is enabled while feedback is disabled, and the flip flop thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the latch stage write port is disabled and feedback is enabled, thereby retaining its present state. Only a single side of the differential stage is used to drive the latch stage and the differential stage may be implemented in an asymmetric fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.