Accelerated low power fatigue testing of FRAM
US7301795B2 · kind B2 · utility
4Cited by
6References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Jan 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.