System and method for avoiding offset in and reducing the footprint of a non-volatile memory
US7301814B2 · kind B2 · utility
0Cited by
22References
14Claims
0Family size
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Key dates
| Filing date | May 11, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | May 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.