Integrated memory having a test circuit for functional testing of the memory
US7302622B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Feb 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of the memory banks. The test circuit includes a data generator for generating read comparison data. A plurality of comparison circuits are assigned to a different one of the memory banks to compare test data read from the assigned memory bank with the read comparison data. A first input of the respective comparison circuit can be connected to the secondary sense amplifier without interposition of the read/write data lines. A second input can be connected to the read/write data lines to receive the read comparison data supplied by the data generator. An output signal of the respective comparison circuit depends on the comparison result of a data comparison of the first and second inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.