Semiconductor memory cell and associated fabrication method
US7304342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/665
Abstract
A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.