Integrated circuit in a maximum input/output configuration
US7305594B2 · kind B2 · utility
0Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2002 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Sep 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.