Partial good integrated circuit and method of testing same

US7305600B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Leonard O. Farnsworth, III · Middlebury, US
• Michael Z. Felske · Colchester, US
• Pamela S. Gillis · Jericho, US
• Benjamin P. Lynch · Colchester, US
• Michael R. Ouellette · Colchester, US
• Thomas St.Pierre · Forstinning, DE
• Tad J. Wilder · South Hero, US
• Carl Barnhart · Tucson, US

Key dates

• Filing date: Aug 29, 2003
• Grant date: Dec 4, 2007
• Expiry date: Jan 25, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/3202
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.