Method of manufacture of a semiconductor integrated circuit device including a plurality of columnar laminates having different spacing in different directions
US7306984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2007 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jan 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.