Three dimensional polymer memory cell systems
US7307338B1 · kind B1 · utility
11Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Sep 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methodologies are provided for forming three dimensional memory structures that are fabricated from blocks of individual polymer memory cells stacked on top of each other. Such a polymer memory structure can be formed on top of control component circuitries employed for programming a plurality of memory cells that form the stacked three dimensional structure. Such an arrangement provides for an efficient placement of polymer memory cell on a wafer surface, and increases amount of die space available for circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.