Integrated memory and method for testing the memory
US7308622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2003 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | May 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal terminal for receiving a further signal, which differs from the command signals. Registers store data patterns or data topologies for use in the test operation of the memory. A register decoder circuit serves for the selection of the registers, it being possible for inputs of the register decoder circuit to be connected to the command terminals and to the signal terminal for the purpose of selection of the registers in the test operation. The invention makes it possible, for the test operation, to address an increased number of registers without driving an additional external terminal pin. A method for testing the memory is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.