Use of redundant routes to increase the yield and reliability of a VLSI layout

US7308669B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Markus Buehler · Holzgerlingen, DE
• John M. Cohn · South Burlington, US
• David J. Hathaway · Underhill Center, US
• Jason D. Hibbeler · Williston, US
• Juergen Koehl · Holzgerlingen, DE

Key dates

• Filing date: May 18, 2005
• Grant date: Dec 11, 2007
• Expiry date: Jun 8, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/39
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.