Quasi self-aligned source/drain FinFET process
US7309626B2 · kind B2 · utility
130Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Mar 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
Abstract
A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.