Electronic device having an interface supported testing mode
US7309999B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Jan 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48139
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.