Annealed wafer and method for manufacturing the same
US7311888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3225
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 μm from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1×109/cm3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.