Non-volatile memory device having page buffer for verifying pre-erase
US7313024B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit lines through a sensing line. Each of the plurality of page buffers may include a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify, and a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.