Semiconductor device
US7313026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Nov 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.