Internally generating patterns for testing in an integrated circuit device
US7313740B2 · kind B2 · utility
26Cited by
94References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Oct 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address signals from the second integrated circuit chip during normal operation. Circuitry on the first integrated circuit chip generates address signals for use in testing the first integrated chip in a test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.