Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors

US7315075B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John M. Aitken · South Burlington, US
• Ethan H. Cannon · South Burlington, US
• Philip J. Oldiges · Lagrangeville, US
• Alvin W. Strong · South Burlington, US

Key dates

• Filing date: Jan 26, 2005
• Grant date: Jan 1, 2008
• Expiry date: Oct 21, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/62

Abstract

Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.