Apparatus and method for selective memory attribute control
US7315921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2002 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Nov 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective override of memory traits at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a memory trait for a memory reference prescribed by the extended instruction, where the memory trait for the memory reference cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and employs the memory trait to execute the memory reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.