Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
US7319603B2 · kind B2 · utility
1Cited by
6References
2Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 4, 2005 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Oct 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.