Ramp gate erase for dual bit flash memory
US7319615B1 · kind B1 · utility
11Cited by
10References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2006 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Aug 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.