Double bumping of flexible substrate for first and second level interconnects
US7320933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Apr 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.