Semiconductor package and method for manufacturing the same
US7321168B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2006 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.