Memory controller with staggered request signal output
US7321524B2 · kind B2 · utility
27Cited by
13References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Dec 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.