Self-aligned cross point resistor memory array

US7323349B2 · kind B2 · utility

Assignee

• Sharp Laboratories of America, Inc. · US

Inventors

• Sheng Teng Hsu · Camas, US
• Jong-Jan Lee · Camas, US
• Jer-Shen Maa · Vancouver, US
• Douglas J. Tweet · Camas, US
• Wei-Wei Zhuang · Vancouver, US

Key dates

• Filing date: May 2, 2005
• Grant date: Jan 29, 2008
• Expiry date: Jul 8, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8836

Abstract

A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.