System with meshed power and signal buses on cell array
US7323727B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 8, 2007 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.