Layout techniques for memory circuitry
US7324364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2006 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Feb 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of VSS planes are interconnected with the switching devices. The switching devices and the VSS planes are formed at a first level. The VSS planes can be formed as substantially complementary interlocking regions that also form functional portions of the switching devices. The switching devices can be connected between an adjacent one of the word lines and a selected one of the bit lines of an adjacent one of the bit line structures for selective electrical conduction therebetween upon activation by the adjacent one of the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.