Phase change memory fabricated using self-aligned processing
US7324365B2 · kind B2 · utility
33Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2006 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Mar 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.