Adder circuit with sense-amplifier multiplexer front-end
US7325024B2 · kind B2 · utility
3Cited by
13References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2003 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Oct 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.