Synchronous signal generator

US7325152B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Paul Wallner · Prien am Chiemsee, DE
• Peter Gregorius · Munich, DE

Key dates

• Filing date: Jun 30, 2005
• Grant date: Jan 29, 2008
• Expiry date: Jul 8, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/107
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.