Test circuit and method for multilevel cell flash memory
US7325177B2 · kind B2 · utility
8Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2004 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Aug 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.