Methods for fabrication of a stressed MOS device

US7326601B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Frank Wirbeleit · Dresden, DE
• Linda Black · Wappingers Falls, US
• Igor Peidous · Fishkill, US

Key dates

• Filing date: Sep 26, 2005
• Grant date: Feb 5, 2008
• Expiry date: Jun 7, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01

Abstract

Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is anisotropically etched to form a first recess aligned with the first edge and a second recess aligned with the second edge. The substrate is further isotropically etched to form a third recess in the substrate extending beneath the channel. The third recess is filled with an expanding material to exert an upward force on the channel and the first and second recesses are filled with a contact material. Conductivity determining ions are implanted into the contact material to form a source region and a drain region aligned with the first and second edges, respectively.