Routing vias in a substrate from bypass capacitor pads
US7326860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2006 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Sep 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0979
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.