Memory device including electrical circuit configured to provide reversible bias across the PMC memory cell to perform erase and write functions
US7327603B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2005 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for programming a programmable metallization cell (PMC) memory cell are provided. A memory device includes a programmable metallization memory cell, a plate line connected to a first node of the memory cell, and a bitline connected to a second node of the memory cell. The memory device also includes circuitry configured to perform a write operation by applying a first voltage to the plate line and a second voltage to the bitline, perform an erase operation by applying the second voltage to the plate line and the first voltage to the bitline, and apply a voltage midway between the first voltage and the second voltage to the plate line when the write operation and the erase operation are not being performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.