High-performance CMOS devices on hybrid crystal oriented substrates
US7329923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2003 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Jun 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.