Test circuitry wafer
US7330040B2 · kind B2 · utility
2Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Dec 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2889
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Method and apparatus for testing a plurality of devices on a device wafer. One embodiment provides a test circuitry wafer having a first surface and a second surface, the test circuitry wafer comprising a plurality of contact pads disposed on the first surface for contacting a plurality of device pads on the device wafer, a plurality of interface pads disposed on the second surface for contacting probe needles on a probe card and one or more test features disposed in the test circuitry wafer, wherein the one or more test features are electrically connected to at least one of the contact pads and the interface pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.